The present invention relates to integrated circuits for data communication systems such as network devices and telecommunications circuits. More particularly, the present invention relates to a multiple channel data buffer for use in an integrated circuit.
Data communication circuits such as network devices and telecommunication circuits typically have several communication channels for connecting to multiple devices such as workstations, telephone and television systems, video teleconferencing systems and other facilities over common data links or carriers. A channel is a logical path from one source to one destination and can be unidirectional or bidirectional. A data routing circuit, such as a direct memory access (DMA) controller, routes data to and from each channel. Each channel includes a data interface controller, such as a serial wide area network (SWAN) controller or a local area network (LAN) controller. Each data interface controller is coupled to the data routing circuit for controlling transmission of its respective data over the data link or carrier.
Data interface controllers are often configured to transmit packets of data having an arbitrary length at a fixed speed. For example, a WAN controller may transmit an Internet Protocol (IP) packet over a fixed speed Interactive Services Digital Network (ISDN) Basic Rate Interface (BRI) using high level data link control (HDLC) framing. Alternatively, a LAN controller such as an Ethernet controller may transmit an IP packet over a fixed speed 10 or 100 Mbps LAN.
In these applications, it is common to use a first-in-first-out (FIFO) memory for buffering transmit and receive data between the DMA controller and each data interface controller. Each communication channel has its own transmit FIFO and its own receive FIFO. Each FIFO uses a dual port random access memory (RAM) for storing the data. One port is used by the data interface controller and the other port is used by the data routing circuit. During a transmit operation, the DMA controller writes the data packets to one end of the FIFO at a DMA transmission rate, and the data interface controller reads the packets at the other end of the FIFO at the rate of the fixed speed data interface.
The FIFO is needed because the DMA transmission rate is generally substantially higher on average than the rate of the fixed speed data interface. Also, the DMA controller is subject to "gaps" in its ability to feed the FIFO because of memory access latencies, contention with other master devices that are coupled to the memory bus and control logic overhead.
The use of multiple transmit FIFOs and multiple receive FIFOs has several disadvantages. For example, each FIFO must have its own address decode logic for writing into the FIFO and reading out of the FIFO. The requirement for multiple address decode logic circuits adds to the number of semiconductor devices or "gates" on the integrated circuit and requires more interconnections to be routed between the gates on the integrated circuit. Each FIFO must also have its own logic for maintaining status flags related to the number of data entries stored in the FIFO, such as an "almost empty" flag and an "almost full" flag. This also adds to the number of gates and interconnections on the integrated circuit. In addition, since each FIFO is a separate module on the integrated circuit, there are more interconnections that must be routed between each FIFO and its source and destination. Improved data communication buffer circuits are desired.